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Comparing hardware computation capability

Tyler Grandahl 3 weeks ago in IQANdesign • updated 2 weeks ago 3

Is there any means of comparing the computational capability of different IQAN hardware?

Basically, how do I know how well or even if an application I want to develop will "fit" on say an MC3 or an MD4 or any other master controllers that all have different hardware limitations and even architectures under the hood?

Is there a means within IQANsimulate to know if a master controller would run out of RAM, or have trouble finishing within the specified cycle time?

Is there any way of providing a high level relative comparison between hardware modules? EG execution time for a standardized function, or a maximum number of channels of a given type? Can you tell me if a MD4 has x time the capability of an MC3 on any axis?

When looking at the processor speed and amount of RAM in the MD4, I'd expect that it'd be fairly hard to overwhelm it. But then again, I have no idea how efficient the internal data structures of IQAN are and how demanding other threads running for the UI might be.

So I've partially answered my own question, all I had to do was read the manual :-). The table shown in the manual comparing Flash and RAM resources is great, but it lists N/A for all MD4 memory parameters with no explanation. Is this because the resources on this unit are so large that its effectively impossible to run out?

The cautionary explanation of RAM usage estimation within sim only being useful as an approximation is good to know. This leaves me wondering though (and I can't find it discussed in the manual anywhere), Is the same thing true of cycle utilization %? Or is cycle utilization % in sim not valid at all? Even if the sim is naturally running at a different rate due to the hardware and operating system differences of the development computer, I would think you'd still be able to calculate exactly how many instructions would be needed for a given execution cycle of the project and how long that would take to execute on the real hardware.

Yes, the abundance of RAM is one reason it is put as NA in the MD4. In a realistic application, you will bump into the limitation of cycle utilization long before you get near the limit for RAM. Another reason is that most of the RAM is used by firmware you as application designer have no impact on, for example the graphics package. 

For the modules that are listed with a value in the RAM column, it is only the RAM reserved for the IQANdesign application that is listed. 

For these masters, the project statistics gives estimated memory utilization.  


Note that it is the statistics you have to look at to see this estimate, simulation with IQANsimulate does not show these values on the system information channels for memory utilization. 


For cycle utilzation, there is no offline estimate, you need to measure on a real system to see this.  You get a good measurement of this just by checking on a standalone master on the bench. There is some impact from CAN traffic in a full system, but the difference quite small.  


Thanks for the clarification Gustav, that all makes sense. It sounds like I'll have to just jump in with some hardware and assume the MD4 is going to be pretty challenging to overload.


Since you mentioned CAN traffic loading. Are there limitations to the amount of CAN traffic the MD4 can tolerate? If I have 100% bus utilization on a 500k bus and all of those messages are used in the MD4 will it miss some? Or as a more realistic scenario, If I have a burst of messages (all with unique IDs) that will come in sequentially as fast as the bus allows, is there risk of missing some?