Does someone knows if it's possible to reset a COUT open load error?

Now the output is disabled when a open load occurs until the system is shutdown and repowered.

Hello, I would like to use a 32-bit real number in big endian, but when I choose real, I cannot select it and it defaults to little endian. Does anyone have a solution?

Description for components are not shows in the project documentation

I just had one of my machines that's running a fairly standard program for us have a watchdog reset. Can anyone tell me from the contents of this screen what might have led to this?

I'm having some difficulty changing the control order in the display page editor in the latest version of Design 6.

The software manual says: 

"To change the order, drag and drop a control, group or layer within the control list."

But when I try to drag items around to change their order I get the circle with a line through it mouse pointer. When you release the mouse button the order numbers haven't changed.

Using IQAN6, we have encountered some unexpected behaviour when using a NOT condition with a Positive Flank condition. A solution has been found but curious as to if this behaviour is in the Simulation only or will the HW behave in the same manner. If this is the expected behaviour, how are these conditions handled at the system level?

Is there a way by using Qcode that I can take a scaled analog input pin, and work with the raw mV values measured at the pin?

As a suggestion, is it possible to throw compilation error when "Allow stop" in security property is tied to channel that executes logic for millisecond intervals. For example, if "Allow stop" is tied to channel that evaluates flank and if not latched then module cannot be re-programmed, unless trying to program without ID tag. 

There is an issue with IQAN7.02 Firmware where the blocking logic and Activating logic is not evaluated in same scan. It seems like activating logic is evaluated in the following scan after the blocking logic goes to false, which misses the flank detection in the activating logic. After running the same logic in older version of firmware, it was found that flank detection was not missed. 

Also, this was tested by using time delay of 100msec for activating logic and it worked fine which leads us to believing that both activating and blocking logic gets evaluated in different scan. FYI - I have 20msec as my application scan cycle time.